Please use this identifier to cite or link to this item: http://hdl.handle.net/11401/75982
Title: A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs
Authors: Cho, Shenghsun
Patel, Mrunal
Kaladagi, Basavaraj
Chen, Han
Palit, Tapti
Ferdman, Michael
Milder, Peter
Issue Date: 2017
Publisher: Department of Computer Science
Series/Report no.: ;CEAS Technical Report; 839
URI: http://hdl.handle.net/11401/75982
Appears in Collections:Technical Reports

Files in This Item:
File Description SizeFormat 
Tech_Report_CEAS_839.pdfTechnical Report 839212.15 kBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.