DSpace Repository

Physically and Logically Reversible Superconducting Circuit

Show simple item record

dc.contributor.advisor Vasili K. Semenov. en_US
dc.contributor.author Ren, Jie en_US
dc.contributor.other Department of Physics en_US
dc.date.accessioned 2012-05-17T12:22:02Z
dc.date.accessioned 2015-04-24T14:48:30Z
dc.date.available 2012-05-17T12:22:02Z
dc.date.available 2015-04-24T14:48:30Z
dc.date.issued 2011-05-01 en_US
dc.identifier Ren_grad.sunysb_0771E_10445.pdf en_US
dc.identifier.uri http://hdl.handle.net/1951/56102 en_US
dc.identifier.uri http://hdl.handle.net/11401/71679 en_US
dc.description.abstract Prior to early this century, the semiconductor microprocessor can be scaled according to the Moore's law, basically doubling its performance in every 18 months. Only recently, the energy efficiency of semiconductor integrated circuits has become a concern than their computational capabilities since their power dissipation scales nonlinear with clock frequency. The specific energy dissipation per logic operation for a modern semiconductor computer is still over 6 orders of magnitude above the thermodynamic threshold k<sub>B</sub>Tln2. It has been known for a long time that this thermodynamic limit on the energy dissipation per logic operation can be overcome by physically and logically reversible circuits. Reversible circuits based on nSQUIDs (negative SQUIDs) or dc SQUIDs (superconducting quantum interference device) with negative mutual inductance between the arms of the SQUID loop, are introduced and investigated in this thesis. First test reversible circuit contains one 8-stage shift register, cells that transfer the input data to the outputs. Dynamic of this circuit illustrates unique properties which agree well with theoretical analysis. Based on the knowledge from the study of shift register, a new timing belt clocking scheme built upon the moving vortices along long Josephson junction (LJJ) is introduced and analyzed. The test circuits for this new scheme contain two 8-stage shift registers, one with direct and the other with inverted outputs. The energy dissipation per nSQUID gate per bit measured for these test circuits at 4 K temperature is already below the thermodynamic threshold. A family of logical gates based on the new timing belt and nSQUIDs shift register are continued to be developed and these gates are capable of fundamentally low energy dissipation and the ability to operate in both irreversible and reversible modes. Moreover, the extremely low energy dissipation in these circuits makes them a natural candidate to support circuitry working in quantum mode with unique advantages. en_US
dc.description.sponsorship This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. en_US
dc.format Monograph en_US
dc.format.medium Electronic Resource en_US
dc.language.iso en_US en_US
dc.publisher The Graduate School, Stony Brook University: Stony Brook, NY. en_US
dc.subject.lcsh Physics en_US
dc.subject.other Reversible computing, Superconducting en_US
dc.title Physically and Logically Reversible Superconducting Circuit en_US
dc.type Dissertation en_US
dc.mimetype Application/PDF en_US
dc.contributor.committeemember Dmitri Averin en_US
dc.contributor.committeemember Gene Sprouse en_US
dc.contributor.committeemember Peter Shkolnikov en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search DSpace


Advanced Search

Browse

My Account