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Digital Implementation of a Synchronous First-in First-out ( FIFO) using CAD tools

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dc.contributor.advisor Stanacevic, Milutin en_US
dc.contributor.author Gupta, Aseem en_US
dc.contributor.other Department of Electrical Engineering. en_US
dc.date.accessioned 2017-09-20T16:52:44Z
dc.date.available 2017-09-20T16:52:44Z
dc.date.issued 2015-12-01 en_US
dc.identifier.uri http://hdl.handle.net/11401/77464 en_US
dc.description 61 pg. en_US
dc.description.abstract Over the past couple of decades, digital design has prospered many miles. The availability of advanced EDA tools help cut design times, debugging issues and time-to-market (TTM). Understanding the digital design flow has now become crucial and many IP cores are being built in no time with use of advanced tools. The tools for front-end, back-end simulations have given industry freedom to experiment new complex designs. The productivity of a digital designer is also a function of his ability to step up of a ramp and use the EDA tools to achieve faster designs and get the job done. Tools such as for synthesis, place and route, and timing verification have evolved over times with many variations and different command tools. Thus, the designer has to adjust with different and multiple UI's (user interfaces). In general industrial design, large CAD (Computer-Aided Design) teams are needed to provide such smoother flow control and results gathering capabilities via extensive scripting[5]. The thesis is based on learning and getting hands-on experience of new cutting-edge tools for faster designs. First-in First-out (FIFO) design is crucial where the data has to be passed across different clock domains. Synchronous FIFO is used for first-in first-out read/write operation through a single clock port. This thesis describes the digital implementation of a synchronous FIFO with front-end and back-end flow using mostly Cadence Design Systems (CDS) and Mentor Graphics Corporation (MGC) EDA tools. Front-end involves logic design and simulation, logic synthesis and functional verification. Floorplanning, automatic placing and routing, clock-tree synthesis, timing closure and physical verification were performed as back-end design steps. The ionizing radiations on a semiconductor device can cause bits to flip thereby changing the functionality of the digital IC causing a phenomenon called Single Event Upset (SEU). Thus, digital integrated circuits used for applications which expose them to radiations need to be SEU-tolerant. Many radiation-hardened-by-design (RHBD) techniques have been developed and one such technique is discussed in this thesis. This technique is called DICE (Dual-Interlocked Cell Storage). As part of my work, drawing layouts and getting familiarized with the Process Design Kit (PDK) was necessary to complete a SEU-tolerant Flip Flop layout. In this process, TSMC 65nm, 130nm and IBM 130nm PDK's were studied and standard cells layouts were drawn. en_US
dc.description.sponsorship This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. en_US
dc.format Monograph en_US
dc.format.medium Electronic Resource en_US
dc.language.iso en_US en_US
dc.publisher The Graduate School, Stony Brook University: Stony Brook, NY. en_US
dc.subject.lcsh Electrical engineering en_US
dc.title Digital Implementation of a Synchronous First-in First-out ( FIFO) using CAD tools en_US
dc.type Thesis en_US
dc.mimetype Application/PDF en_US
dc.contributor.committeemember Geronimo, Gianluigi. en_US


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