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Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability

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dc.contributor.advisor Salman, Emre en_US
dc.contributor.author Noor, Tasnuva en_US
dc.contributor.other Department of Electrical Engineering en_US
dc.date.accessioned 2017-09-20T16:52:47Z
dc.date.available 2017-09-20T16:52:47Z
dc.date.issued 2016-12-01 en_US
dc.identifier.uri http://hdl.handle.net/11401/77481 en_US
dc.description 44 pgs en_US
dc.description.abstract A novel glitch-free integrated clock gating (ICG) cell is developed and demonstrated in 45 nm CMOS technology. The proposed cell is more reliable as it produces an uninterrupted gated clock signal in cases where glitches occur in the enable signal during clock transitions. A detailed comparison of the proposed cell with the existing integrated clock gating cells is also presented. Glitch-free operation (and therefore high reliability) is achieved at the expense of larger power and delay, as quantified for 45 nm CMOS technology. Several design issues and different glitch characteristics are also discussed. The proposed ICG cell is shown to be highly applicable to dual edge triggered flip- flops where existing ICGs fail if there are glitches in the enable during clock transitions. en_US
dc.description.sponsorship This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. en_US
dc.format Monograph en_US
dc.format.medium Electronic Resource en_US
dc.language.iso en_US en_US
dc.publisher The Graduate School, Stony Brook University: Stony Brook, NY. en_US
dc.subject.lcsh Electrical engineering en_US
dc.subject.other Clock Gating, Dual Edge Triggered Flip-flop, Integrated Circuit Design, Integrated Clock Gating Cell, Low Power Design, VLSI en_US
dc.title Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability en_US
dc.type Thesis en_US
dc.mimetype Application/PDF en_US
dc.contributor.committeemember Hong, Sangjin en_US


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