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High Performance Partition Based Reconfigurable Platform for Multiple Concurrent Applications

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dc.contributor.advisor Hong, Sangjin en_US
dc.contributor.advisor Milder, Peter en_US
dc.contributor.author Qi, Qi en_US
dc.contributor.other Department of Electrical Engineering en_US
dc.date.accessioned 2017-09-20T16:52:47Z
dc.date.available 2017-09-20T16:52:47Z
dc.date.issued 2015-12-01 en_US
dc.identifier.uri http://hdl.handle.net/11401/77483 en_US
dc.description 215 pgs en_US
dc.description.abstract Reconfigurable architectures, combining the benefits of flexibility and high performance, are suitable for embedded digital signal processing. However, it is critical to bridge the gap between application algorithms and their implementation. Further, low power design is critical, but it is difficult to migrate an existing algorithm into a data-centric application that is represented as a dataflow and to map this to a reconfigurable architecture. Thus, such a reconfigurable platform mapped from application dataflow graphs and an architecture-aware optimization algorithm become necessary. This thesis proposes an efficient algorithm to optimize the clock frequencies of the processing elements in a reconfigurable architecture, finding the frequency configuration that minimizes the power consumed while meeting the application's timing requirements. The algorithm takes as input a dataflow representing the intended application characteristics and the required timing constraint information, and optimizes the frequency configuration by dynamically exploiting correlation between frequencies and iteration time in consideration of parameter variation to avoid data collision or loss. Then it proposes a novel hardware reconfigurable platform divided into multiple partitions, where each partition is entirely buffer-centered consisting of a large number of heterogeneous processing elements operating with buffers through reconfigurable interconnect, to execute multiple concurrent applications. Depending on performance requirements, an application migrated from a dataflow graph can be mapped to more than one partition interacting through bridge buffers. To accommodate asynchronous clock configuration, this platform uses flexible hierarchical controller design. The controller considers execution flow and structural configuration separately but collaboratively for dynamic reconfiguration of the dataflow. The use of a tree structured controller makes the design scalable. We model the proposed reconfigurable platform and hierarchical controller in SystemC, and implement the frequency optimization algorithm to provide clock frequencies that minimize power consumption to such platform. Experiments shows that this algorithm achieves power consumption that is typically equal to a simulated annealing-based method, while running 100 times faster on average. The SystemC simulations demonstrate the controller is able to load and execute applications with dynamic reconfiguration. Therefore, the system can map multiple processing elements onto a single core and switch between them during run-time. en_US
dc.description.sponsorship This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. en_US
dc.format Monograph en_US
dc.format.medium Electronic Resource en_US
dc.language.iso en_US en_US
dc.publisher The Graduate School, Stony Brook University: Stony Brook, NY. en_US
dc.subject.lcsh Electrical engineering en_US
dc.subject.other Buffer based dataflow, Dynamic reconfiguration, Frequency selection, Hierarchical controller, Reconfigurable architecture en_US
dc.title High Performance Partition Based Reconfigurable Platform for Multiple Concurrent Applications en_US
dc.type Dissertation en_US
dc.mimetype Application/PDF en_US
dc.contributor.committeemember Shterengas, Leon en_US
dc.contributor.committeemember Ahn, Hongshik en_US

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